C, Opengl, Opencl, D3D, Uvm, systemverilog

C, Opengl, Opencl, D3D, Uvm, systemverilog

code coverage , Python, C, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

Verilog, random stimulus, VMM, assertion-based verification, Uvm, systemverilog, functional coverage, advanced verification methodologies

simvision , Hspice, SPICE testbenches at Block Fullchip Level, Finseim, Xcellium, Scripting skills using perl, MS RVM model writing, verilog a, SV PSL assertions, Analog and Mixed signal Verification, DRAM memory related fields, Analog mixed signal circuits, virtuoso, Verilog Models, Waveview, Debugging complex Analog Digital Mixed-Signal circuits, COSIM Mixed signal verification environment, SV UVM based Verification, primesim

MATLAB, Dsp, DDR IP cores, SV UVM based test benches, C language programming, system level design, verification IPs, Siemens verification tools, AMBA protocols