redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

Implementation of Arm cores systems and SoCs, Physical Design, Synthesis, Automation Python, Timing Closure, Low power design techniques, Verilog RTL design, LEC CLP and ECO implementation, Timing Constraints development

Static Timing Analysis, Python, Tcl, SDC constraint authoring and management, primetime, Fusion Compiler, Physical-Aware Synthesis

Electromigration (EM) analysis, Shell scripting, Cadence Voltus, Ansys RedHawk, Signoff methodologies, Automation flows, Physical Design flow, Extraction, floorplanning, Placement, Power integrity analysis, CTS routing, IR drop analysis

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities