static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

Functional Design, Problem Solving, Design For Safety and Reliability, Mechanical Design, Electromechanical Engineering, Computer Aided Design, Electrical Safety

bandgap references , Current Mirrors, Transistor level architectures, Simulation and verification, Schmitt Trigger, ESD protection circuits for CMOS IC, Transistor layout fabrication process, Amplifiers, Analog Circuit Design, Level Shifter, Schematic generation, High voltage design rules, LDMOS, Comparators, Power FET technology, MOS Diodes, Mismatch and Monte Carlo analysis

bandgap references , temperature sensors , Dll, Process Monitor, AI proficiency, Parasitic modeling, design validation, verification processes, Oscillators, Claude, agentic AI models, modeling and simulation, Comparators, Analog Test Mux, Charge Pumps, CMOS Amplifiers, IO Buffers, LDOs