simvision , C, C++, Ovm, Front End Web Development, PERL, UI, Verilog, Python, Tcl, VMANAGER, SystemVerilog Assertions, Verdi, Uvm, Synopsys VCS, Incisive Xcelium, VMM, Coverage management, Modelsim

System Verilog, X86, CPU Core Verification, Coverage models, Constrained-random tests, Scoreboards, Checkers, Uvm, Testbenches, RISC-V, ARM ISA, ISA behavior

Ovm, Debugging, Unix Shell Scripting, Verilog, System Verilog, Perl, Pcie, Tcl Scripting, DDR, Circuit Analysis, Uvm, IC chip design development flow process, CAE CAD tools, Circuit Design, test bench development, VHDL, AHB, Axi, CMOS logic design, CMOS device operation and characteristics, coverage assertion driven verification, verification plans, Simulation

Java, Software Development Life Cycle, Golang, Gcp, Agile Methodologies, Azure, Kubernetes, AWS, AI-assisted software development tools, cloud-native solutions

state management , Python Scripting, PowerShell, Bash, Waf, Azure, Kubernetes, Key Vault, scopes, VNets, CI CD, GitHub Actions, Entra ID Federation, Terraform Module Authoring, Keycloak, VPN Gateway, Azure Policy Governance, Azure Networking, AKS, Token Lifetimes, Front Door, Curity, Private Endpoints, Client Registration