Your Role

Lead DFT execution across IP and SoC programs from architecture to silicon production.
Define and implement Scan, Scan Compression (EDT), ATPG, MBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG) solutions.
Drive scan insertion, DFT integration, and sign-off using industry-standard EDA tools.
Generate and optimize ATPG patterns to achieve high fault coverage and production test goals.
Perform DFT DRC checks, coverage analysis, and debug scan, compression, and ATPG issues.
Develop and validate STA constraints for various test modes.
Support silicon bring-up, failure diagnosis, yield improvement, and production ramp activities.
Collaborate with RTL, Verification, Physical Design, Product Engineering, and Manufacturing teams to resolve test-related challenges.
Develop automation solutions using TCL, Perl, Python, and Shell scripting to improve productivity and quality.
Mentor junior engineers, drive technical excellence, and contribute to DFT methodology improvements across programs.

Your Profile

15 to 20+ years of hands-on experience in Design-for-Test (DFT) for ASIC and SoC development.
Proven experience leading end-to-end DFT implementation for multiple successful SoC tape-outs.
Strong expertise in Scan Insertion, Scan Compression (EDT), ATPG, MBIST, LBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG).
Hands-on experience with Synopsys TestMAX/DFTMAX, TetraMAX, Fusion Compiler, Siemens Tessent Suite, or Cadence Modus tools.
Deep understanding of fault models including Stuck-at, Transition, Path Delay, Bridge Fault, and Cell-Aware ATPG methodologies.
Experience in DFT verification, DRC closure, ATPG pattern validation, and fault coverage optimization.
Strong knowledge of timing constraints, STA for test modes, clocking architectures, and low-power DFT methodologies.
Experience supporting silicon bring-up, tester debug, diagnosis, yield improvement, and production ramp activities.
Proficiency in TCL, Perl, Python, and Shell scripting for automation and methodology development.

Work with some of the world's leading semiconductor and technology companies on cutting-edge ASIC, SoC, AI, Automotive, Networking, and HPC programs.
Gain exposure to the complete silicon lifecycle, from architecture, design, verification, DFT, physical implementation, tape-out, silicon bring-up, and production support.
Collaborate with globally distributed engineering teams across North America, Europe, and Asia.Access continuous learning opportunities through Capgemini's training, certification, and technical upskilling programs.