Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5

Svn, C, Shell, Tcl, Verilog, Python, Perl, Git, systemverilog, Cadence Verisium Manager, Uvm, VHDL, Cadence Xcelium

CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration, Layout Design

Shell, Svn, C, Tcl, Verilog, Python, Perl, Git, Cadence Verisium Manager, Uvm, systemverilog, VHDL, Cadence Xcelium

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP