About Us

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve's design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve's Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolve's clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

For more details, visit https://www.tessolve.com/

**Job Overview**

An experienced Static Timing Analysis (STA) Engineer responsible for STA and timing sign-off for complex SoC/ASIC designs, collaborating across RTL, synthesis, physical design, and verification teams. Key responsibilities include timing closure, developing SDC constraints, performing timing ECOs, clock and skew analysis, and supporting tape-out and foundry sign-off requirements. Required skills include hands-on use of STA tools (PrimeTime, Tempus, or equivalent), scripting for automation, MMMC analysis familiarity, and knowledge of synthesis and physical design flows. This role adds value by ensuring robust timing convergence and reliable silicon delivery for advanced technology node projects. Job location: Not specified; suitable for semiconductor/ASIC/SoC engineering teams.

Job Designation**: STA Engineer
Years of Exp**: 7+ years
Job Location**: Not specified

**What you'll do**

Perform block- and full-chip static timing analysis and timing sign-off tasks.
Develop and maintain SDC constraints for pre- and post-layout stages.
Analyze timing reports and debug setup, hold, and transition violations.
Execute timing ECOs for functional and test modes as required.
Drive timing closure across multiple PVT corners, modes, and scenarios.
Conduct clock tree, skew, and path optimization analyses.
Coordinate with RTL, synthesis, physical design, and verification teams.
Support tape-out activities and interface with foundry for sign-off.

**Who you are**

Proficient with STA tools such as PrimeTime, Tempus, or equivalents.
Knowledgeable of SDC constraints, timing checks, and ECO methodologies.
Familiar with multi-mode multi-corner (MMMC) timing analysis.
Comfortable with synthesis and physical design flows and implications.
Skilled in scripting (Tcl, Perl, Python, or Shell) for automation tasks.
Experienced with complex SoC/ASIC designs at advanced technology nodes.
Strong debugging, analytical thinking, and problem-solving capabilities.
Able to work independently and lead timing closure efforts effectively.
Familiarity with low-power UPF flow, library characterization, or SI helpful.

Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries (Tessolve) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at [HIDDEN TEXT]. Tessolve is not responsible for any losses incurred due to such fraudulent activities

Sr. Design Engineer 2