simvision , Hspice, SPICE testbenches at Block Fullchip Level, Finseim, Xcellium, Scripting skills using perl, MS RVM model writing, verilog a, SV PSL assertions, Analog and Mixed signal Verification, DRAM memory related fields, Analog mixed signal circuits, virtuoso, Verilog Models, Waveview, Debugging complex Analog Digital Mixed-Signal circuits, COSIM Mixed signal verification environment, SV UVM based Verification, primesim