Real Number Modeling, Verification Coverage Analysis, coverage analysis, Cadence Xcelium, Mixed-Signal Testbench Development, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, PLL Verification, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Mixed-Signal Simulation, Simulation Debugging, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Verilog-AMS, AMS Verification, Cadence Virtuoso, AMS Verification Methodology, Cadence ADE Assembler

SystemVerilog UVM, Synopsys VCS, SV-RNM, Verilog-A, Verilog-AMS, Spectre, Cadence Xcelium

monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Verification Automation, Mixed-Signal Debug, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Verilog-A, Cadence

simvision , Cadence Xcelium, AMS SPICE, DMSO, verification planning, testcase creation, testbench development, Verisium, simulation debug, Cadence Virtuoso, Xps, Spectre UltraSim, analog mixed-signal simulation

Register models and firmware interaction, Calibration and link training flows, SerDes PHY architectures, Uvm, systemverilog