GAA (Gate-All-Around), Design Automation, Co-optimization of PDK components, PDK enablement, Spice model understanding, Process design interaction, CMOS device physics, Cadence-based tool suites, Electrical studies, Parasitic Extraction, Physical verification decks, Foundry PDK enablement, Planar MOSFETs, Automation methodology, FinFETs, Semiconductor technology analysis

Physical Verification EDA, DRC, PDK enablement, LVS, Spice models, Cadence-based tool suites, Parasitic Extraction

layout editing tools in the Cadence Virtuoso design environment, CMOS Circuits, chip-level floorplanning, chip-level integration verification, tape-out, BiCMOS circuits, DRC LVS and ERC debugging using Cadence PVS or Mentor Calibre, productivity-enhancing tools and design scripts, analog block integration