hardware engineering , Perl Scripting, Tcl, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design, Physical Design, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

power optimization , static timing analysis, routing, Verilog, Synthesis, power distribution analysis, submicron process node technologies, power delivery methodologies, Power Estimation, reliability verification, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Embedded C, Embedded Operating Systems, CPU architecture, Programming In C, complex system debug, coherent fabric, CPU validation, bare metal programming, CPU uArch, debug infrastructure