Debugging, C, Shell, Tcl, Verilog, System Verilog, Python, Perl, UVM methodology, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

rtl verification , code coverage , Shell scripting, Python, Tcl Scripting, Uvm, Cadence JasperGold, Siemens QuestaSim, Assertion-Based Verification SVA, Functional Coverage, systemverilog, Constrained Random Methodologies, Synopsys VCS, Synopsys VC Formal, Cadence Xcelium

Verilog, System Verilog, Unix Shell Scripting, Oop, Embedded C, Specman e, VHDL, Uvm