PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Linux, Perl, Python, Tcl, Physical Design, EDA Tools, Design Automation, Cadence, Synopsys, Cad Methodology

Tcl Scripting, Perl, Shell scripting, Python, CTS, primetime, Fusion Compiler, floorplanning, Tempus, Cadence Innovus, signoff, Power Planning, Physical Verification, routing optimization, Eco, Timing Closure, Placement, RTL-to-GDSII Physical Design flow, Synopsys ICC2

Sqlalchemy, Nosql, Rabbitmq, Celery, Docker, Reactjs, Agile, FastAPI, Restful Apis, Python, Sql