Java, Ml, C, Scala, Cloud Infrastructure, Python, Go, Ai, Observability, Tooling

PostgreSQL, Kafka, Core Java, Distributed Systems, Openshift, Python, Raid, Redis, Couchbase, Kubernetes, Etl, multi-agent orchestration, no-code low-code UI, vector databases, Llm, LangGraph, LangChain, CrewAI, agent evaluation, ClickHouse, context memory management, AutoGen, backend architecture, RAG, function calling, safety and observability practices

Python, Rtos, Linux, Embedded software architecture, C/C++, AI development environments

Golang, Distributed Systems, Containers, Technical Leadership, Automation, File Systems, Microservices, Cloud Storage, Infrastructure Services, Databases, Gcp, Scalability, Rest Apis, Azure, Python, Kubernetes, AWS, Software Systems Engineering, Go, Security, Reliability, Observability

Garbage Collection, Nvme, Test Strategies, Pcie, Python, Automated reporting systems, Wear levelling, SSD NAND architecture, Qualification methodologies, Test infrastructure, Error Handling and Recovery Flows, Reliability and Endurance Validation, Quality dashboards, Bad block management, Embedded Firmware development, Validation plans, Error injections, NAND Management, Cloud SSD specifications

C, Performance Modeling, Python, System-level tradeoff analysis, behavioral modeling, Architectural validation

Cloud Security, Network Security, PowerShell, Routing, Dns, Zscaler, BGP, Pki, Terraform, Rest Apis, Azure, Tls, Python, Zero Trust, Zscaler AI Firewall

Electromigration (EM, Tcl, Python, Perl, Automation Frameworks, Physical Design and Methodology, Timing Closure, Fusion Compiler, Synopsys DSO.ai, Sub-3nm device physics, primetime, Dynamic IR drop, Crosstalk challenges, Flows-as-Code, Standard Cell SRAM library architectures, Tape-out experience with TSMC N3, CPU micro-architecture, Cerebrus, IC Compiler II, Synopsys Fusion Design Platform

Sta, Scripting flow deployment for SoC Blocks, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Die file generation, SoC Full-chip floorplanning, RDL knowledge, Feed-through planning, Hierarchical design implementation, PnR implementation

clocking , Perl, Python, Verilog, EDA tools for synthesis, LINT, cdc, RDC, VHDL, Use of AI for design, and static timing analysis, Digital IC ASIC design, SoC development flows, SoC-level design and integration, Synthesis flows, Functional Verification, Rtl Design, spyglass, Verification methodologies, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Simulation, Timing Analysis