Dll, Dac, ADC, FinFET process technologies, Voltage detectors, Oscillators, Deep sub-micron technologies, Mixed Signal Design, Mixed-mode simulations, Voltage and current references, Pll, Simulation of analog blocks, power management, Clock management, Statistical simulations, Switching regulators, Signal Processing

bandgap references , PLLs, mixed-signal architectures, post-layout verification, DC-DC converters, BCD processes, Bias Circuits, Comparators, SAR ADCs, corner analysis, LDOs, noise mismatch stability analysis, Voltage References, parasitic effects, matching common-centroid structures, Oscillators, feedback systems, layout concepts, Spectre, Monte Carlo simulations, Analog Mixed-Signal IC Design, Buck regulators, analog floorplanning, Cadence Virtuoso, low-power design techniques

DFE, Duty Cycle Correction, BGR, Oscillators, High-speed clock distribution, Rx CDR, Tx Serializer Output Driver, CTLE, Generic Analog Circuits, Analog Circuit Design, EDA Tools, Bias Circuits, Deserializer, Circuit design simulation and analysis, LDO, Lower Nodes Experience, Amplifiers, VGA, Comparators, Power Management Circuits, High-Speed SerDes Tx and Rx blocks

Cadence Virtuoso, Mixed-Signal IC Design, High-Speed ADC Design, Analog IC Design

UNIX, signals systems and transforms, MOS transistors, Analog Circuit Design, layout tradeoffs, layout verification tools, device physics, High Volume Manufacturing, feedback systems, Mixed Signal Design, AC DC analysis, circuit simulation tools, CMOS Bi-CMOS fabrication processes, poles zeros compensation, loop dynamics, Modeling Tools, end-to-end design flow

Spectre, Analog Design, Cadence Virtuoso, Post layout parasitic back-annotation

High-speed SERDES IO PHY Layout design, Analog IO design principles, Signal integrity issues, Automated PnR, CMOS and FinFET technologies

C, Perl, Python, Tcl, mixed-signal circuit design, SPICE simulation, IC layout, verilog a, Analog Circuit Design