boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Gate level simulation debugging, Scan and BIST architectures, Tessent, JTAG protocols, ATPG, EDA Tools, TestMax

boundary scan , Tcl, Vcs, System Verilog, Python, Perl, Logic Equivalency checking, TestMax, EDA Tools, Memory BIST, JTAG protocols, ATPG, Scan and BIST architectures, primetime, Gate level simulation debugging, Tessent tool sets, TetraMax