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ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco Home
Bengaluru, India

Skills:

Perl, Python, System Verilog, Test benches, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

Early Applicant

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

CISCO Credit
Bengaluru, India

Skills:

boundary scan , Perl, System Verilog, Python, Tcl, scan architecture, MBIST, DVE Verdi, JTAG protocol, Uvm

Early Applicant

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

Cisco Live
Bengaluru, India

Skills:

boundary scan , Perl, System Verilog, Python, Tcl, scan architecture, MBIST, DVE Verdi, JTAG protocol, Uvm

Early Applicant

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

Cisco DevNet
Bengaluru, India

Skills:

boundary scan , Perl, Python, System Verilog, Tcl, scan architecture, MBIST, JTAG protocol, DVE Verdi, Uvm

Early Applicant
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