boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

boundary scan , Tcl, Vcs, System Verilog, Python, Perl, Logic Equivalency checking, TestMax, EDA Tools, Memory BIST, JTAG protocols, ATPG, Scan and BIST architectures, primetime, Gate level simulation debugging, Tessent tool sets, TetraMax