Clock tree synthesis (CTS), redhawk , Static Timing Analysis (STA), Python, Perl, Tcl, primetime, Fusion Compiler, ICC2, Power integrity analysis, Tempus, LVS, Voltus, Innovus, Calibre, DFT implementation, Placement, Power Planning, Routing optimization, floorplanning, Physical Verification, Timing closure techniques, DRC, PDN optimization

power optimization , Unix, static timing analysis, Perl, Linux, Shell scripting, Python, Tcl, power analysis, Application Engineering, backend implementation, timing optimization, benchmarking environments, Physical Design, EDA tool development, digital ASIC implementation flow, Timing Closure, Product Validation, automation regression, advanced process technologies

Routing, CTS, Timing Constraints, Placement, physical design flows, Ai, SDF generation, SI closure, STA signoff

Routing, CTS, Timing Constraints, physical design flows, Placement, Ai, SDF generation, SI closure, STA signoff