Multi-patterning, FinFET process nodes, Parasitic Extraction, Layout automation and APR methodologies, Power delivery and signal integrity, Restricted design rules, Device orientation matching rules, Layout-dependent effects, Analog mixed-signal layout techniques

Cadence Tools, DRC LVS checking flows with Calibre, FinFET process technologies

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings