buckling , Solid Mechanics, ut, Heat Transfer, Rt, Pt, Hoop stress, MPI, API 6A, Fluid Dynamics, Design Analysis, API 1104, Flexibility, Burst, PAUT, NACE MR 0175, Fatigue, ASME IX

simvision , Python, Perl, Tcl, Standard Cell design, Finefet planner, Liberate, ICC2, Solido Analytics, AI-assisted tools, FINESIM, HSIM, lib release, DTCO development, layout and verification, VerilogHDL, block level timing analysis, Siliconsmart, CMOS device physics, CMOS Circuit Design, Skill, primetime, Hspice, RTL GDS flow setup, Cadence Virtuoso

power optimization , Verilog, Spi, C, Uart, C++, Ethernet Switching, Tcl, Python, Synthesis, Simulation, FPGA emulation, Timing Closure, Pre-silicon system validation, Area optimization, Microcontroller-based subsystems, systemverilog, Digital design methodologies, I²C, Packet processing, Timing Analysis, TSN