Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout

SPICE-based simulators, ESD design methodologies, IBIS model generation, Package-aware simulations, Signal integrity analysis, Cadence Virtuoso

transistor-level design and simulation, PEX, post-layout verification, LVS, noise analysis, Analog Circuit Design, Spectre, advanced CMOS technology nodes, DRC, layout sensitivity, linearity matching, mixed-signal IC design, Cadence Virtuoso

Scripting, standard cell characterization, Design Verification, SPICE-level circuit simulators, transistor-level circuit design, process variability, circuit behavior, transistor-level device physics, PPA trade-offs, EDA Tools, static CMOS circuits, standard cell characterization tools, layout effects, MOSFET electrical characteristics

C, MATLAB, Python, Perl, Parasitic Extraction, systemverilog, Verilog-A, RF ADE, Spectre, Mixed-Signal Verification, CMOS, Cadence Virtuoso, SERDES

C, Python, Perl, MATLAB, Parasitic Extraction, High-speed SerDes circuits, systemverilog, Mixed-signal verification, Verilog-A, Cadence Virtuoso, RF ADE, Spectre

routing, VCAR auto routing, Cadence Design Suite, Assura Calibre PVS, QRC extraction, IC617 Virtuoso tools, constraints-driven layout, BCD technology, Modgens, Clones, schematic driven layout design, Analog IC layout and verification tools