lifecycle management , Performance, DevSecOps, Machine Learning, AWS, Data Analytics, Cybersecurity, distributed application architecture, CI/CD, interoperability, cloud-native architecture, infrastructure as code, Reliability, enterprise integration patterns, cloud platforms, platform engineering, event-driven architecture, enterprise architecture practices, data platforms, observability, hybrid or SaaS operating models, integration patterns, FinOps

Cybersecurity, Verification And Validation, Requirements Engineering, Systems engineering, Design Reviews, system decomposition, Power Electronics, technical risk management, Rca, hardware platforms, FTA, Reliability Analysis, real-time systems, Embedded Systems, Safety, Dfmea, industrial communications, multidisciplinary product development, safety-critical products, control sensors, interface definition, architecture methods, complex physical systems, Project Estimation

design integration of SoC systems, verification experience, HW RTL development, performance analysis of complex hardware-software systems, CHI protocols

Performance Modeling, performance debug flows, performance test suites, hardware performance counter monitoring tools, Simulation Tools, correlation techniques, CPU microarchitecture, x86 ISA, ML AI techniques, workload optimization, performance triage tools, performance metrics, performance profiling tools, performance analysis tools, emulation platforms, system-level performance verification, Performance Analysis

Nunit, Spring Boot, SQL Server, Threat Analysis, MySQL, Spring MVC, Oracle, Restful Services, Spring Security, Can, Business process modeling, Angular 16, J2534, System design architecture modeling, cloud-native Azure, Risk Assessment, Security architecture concepts

code coverage , Embedded Firmware, Rtos, Static Analysis, Iso 13485, Risk Management, Iso 14971, IEC 62304, Regulated Medical Device Software

ISO 26262 documentation standards, Ethernet PHY, ESD protection strategy, chip-level signal integrity, HSPHY, jitter budgets, high-speed serial interfaces, eye diagram analysis, high-speed interface architecture, IO ring architecture, power delivery requirements, LPDDR memory PHY, reference clock architecture, PHY placement constraints, SERDES