Python Scripting, System Verilog, BFM models, GPU emulation

Perl, Verilog, Python, Tcl, Cadence Palladium, RTL, Digital Design, emulation compile mapping, systemverilog, acceleration, ASIC SoC emulation, UVM-based verification environments, Synopsys ZeBu, runtime concepts, partitioning

DDR, Automation Frameworks, Ethernet, emulation methodologies, hardware software co-design, emulation testbenches, emulation models, PCIe protocols, ARM Cores, FPGA architecture

Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog

SoC-level DV, Performance optimization, ZEBU Emulation platforms, systemverilog

C, Fpga, Usb, Embedded C, Linux, BIOS, Pcie, Uefi, emulation verification, Memory subsystem, Security Protocols, SoC IP level Power Management flow, SoC Verification, ARM SoC Architecture, Windows Operating Systems, emulation platforms, Validation, high speed IO peripherals, low power design, Pre-Silicon Validation Experience, NPU, power management

Debugging, Scripting, Security Architecture, High-speed protocols, emulation platforms, Boot flow, SoC emulation, Memory interfaces, Peripheral interfaces