arm architecture , C, Firmware, Soc Architecture, Verilog, Embedded Software, Python, Perl, Assembly, CPU architecture, Emulation, systemverilog, AMBA protocols, Simulation

Usb, Perl, Verilog, Sata, Python, VMM, PCI Express, Uvm, systemverilog

Makefile, Windows, Pcie, Perl, Linux, Verilog, System Verilog, IP level ASIC verification, LLMs, AI Agents, HLS tools, UVM testbenches, DMA verification, Simulation profile efficiency improvement, UVM based verification frameworks, CXL

PCIE protocol - Gen3 and above, Usb, Perl, Verilog, Sata, Python, Industry standard verification tools for simulation and debug, CXL-based designs, DV methodologies, PCI Express, Uvm, systemverilog, Functional coverage based constrained random verification, VMM