Perl scripting, System Verilog, designing with multiple power domains and islands using UPF, primetime, RTL design in Verilog, DFT technologies, Synopsys Design Compiler, DFT flows, Windows environments

Windows, Perl scripting, Version Control Systems, Linux, Verilog, System Verilog, Python, Tcl, DFT technologies, SOC design, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Timing Constraints, Synopsys Design Compiler, ASIC Design, Questa CDC, VCS simulation