C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

Makefile, Verilog, Ruby, System Verilog, Oop Concepts, Perl scripting, CPU architecture, Assembly language programming, Digital Design, Asic Design Verification, JTAG protocols, Debugging firmware, Rtl Design, Verification flows, Post-silicon debugging

Verilog, Tcl, System Verilog, Python, Perl, CHI, UVM-based testbenches, Mentor Questa, Ace, AMBA, Synopsys VCS, VHDL, RISC-V instruction set architecture, APB, Axi, Cadence Xcelium