Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Verilog, Tcl, System Verilog, Python, Perl, CHI, UVM-based testbenches, Mentor Questa, Ace, AMBA, Synopsys VCS, VHDL, RISC-V instruction set architecture, APB, Axi, Cadence Xcelium

C, Jtag, Verilog, Scripting Languages, System Verilog, IEEE1500, HDLs, memory dump, advanced verification techniques, MBIST, scan dump, formal verification methodologies, CPU micro-architectures, Dft, CPU architectures, power management features