static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Cassandra, PostgreSQL, Spring Boot, Microservices, Rest Api, Nosql, React, MySQL, Javascript, Python, AWS, Java, Sql, Figma, Gcp, MongoDB, Azure, Opik, Claude, LangGraph, Multi-Agent Systems, evals, Traces, Langsmith

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

Elasticsearch, Spring Boot, Java, Microservices, Kibana, RDBMS, Grafana, Postgres, Reactjs, Kafka, Redis, Oracle, Kubernetes, Python, Nosql, Docker, Git, Workflow automation, Event-driven architecture, Github Actions, Time-series DBs, GraphDB

Azure - AKS, Python, Sql, Github, Docker, Arm

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification