Perl, Python, Tcl, DFx methodologies, Design Compiler, Fusion Compiler, BSCAN, MBIST, DFX Design Architect, SSN, spyglass, Tessent, ATPG, Scan, TestKompress, IJTAG

Perl, Python, Tcl, DFx methodologies, Fusion Compiler, BSCAN, MBIST, DFX Design Architect, SSN, ATPG, Scan, IJTAG, Design Compiler, spyglass, Tessent, TestKompress

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM

Perl scripting, Delay Faults, Pattern Simulation, Siemens Tessent, Transition Faults, Synopsys TestMAX, Pattern Generation, DFT Compiler, Scan Insertion, DFT implementation, DFT DRC violations, ATPG, Cadence Modus, Stuck-at Faults