Debugging, Perl scripting, Cadence Tools, Innovus, RTL2GDS, IP QA, Mentor Calibre, Apache RedHawk, Genus, Synopsys Prime Time, CMOS circuit design fundamentals

Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, ICV, Synopsys

Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Routing, Shell Scripting, Tcl, Sta, Signoff, CTS, floorplanning, EM, Synopsys Fusion Compiler, Ir, LVS, FC Innovus, Physical Verification, MMMC, Timing Closure, Placement, DRC

Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop

static timing analysis, Python, Tcl, primetime, Tempus, high-speed design timing convergence, constraints synthesis, Clock Tree Synthesis, ECO flows

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff