C, Performance Modeling, Python, System-level tradeoff analysis, behavioral modeling, Architectural validation

Electromigration (EM), Perl, Automation Frameworks, Python, Tcl, Tape-out experience with TSMC N3, primetime, Fusion Compiler, IC Compiler II, Synopsys DSO.ai, CPU micro-architecture, Cerebrus, Timing Closure, Standard Cell SRAM library architectures, Synopsys Fusion Design Platform, Physical Design and Methodology, Flows-as-Code, Sub-3nm device physics, Dynamic IR drop, Crosstalk challenges

static timing analysis, EDA tools for synthesis, digital design principles, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, RTL quality tools such as Spyglass Lint CDC RDC

Python, Xcelium, SystemVerilog-RNM, Uvm, Spectre, Synopsys VCS, Cadence Virtuoso, Ansys Lumerical, Verilog-AMS, analog mixed signal verification, Synopsys OptoCompiler, Skill, FineSim, optical simulation tools

C++, Linux, Bash, Python, Kubernetes, CI/CD