System Verilog, CPU Core Verification, Scoreboards and Checkers, Uvm, ISA-level Validation and Compliance Testing

.NET, Angular, Vue.JS, Version Control Systems, Rest Apis, AI-assisted development tools

Nosql, RDBMS, DevOps Tooling, Microservices Architecture, Frontend Engineering Paradigms, Distributed Queuing Systems, Generative AI Tools

Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

Unit Testing, Uart, Ethernet Protocols, Spi, I2c, Logic Design, ASIC design flow, Synthesis, digital design concepts, Communications, gate level simulations, high speed design, backend, functional safety design, MIPI, Synthesis, Verification, HDMI, Timing, LINT, front end implementation tools, Equivalence Check, cdc, DP, Sta, ASIC synthesis constraints, Power estimation tools, IP level verification

workflow engines , Java, Distributed Systems, AWS, Python, Scala, Shared Services, OAuth 2.0, LLMs, orchestration systems, multi-agent systems, cloud-native software systems, agent frameworks, reusable runtime frameworks, event-driven architectures, platform infrastructure, AI models, AI orchestration tools, internal developer platforms

Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim