Logic Design, shell scripting, Perl, System Verilog, Tcl, Cadence Tools, physical aware synthesis, HDL – Verilog, Logic Synthesis, Synthesis, formal verification, low power design, Physical Design, Timing Closure, EDA Tools, Genus Synthesis Solution

Jira, Pcie, SFDC, Ethernet, Test Methodologies, Sta, ADC, Tx and Rx Equalizers, Phase Locked Loops, Noise, board design, gate level verification, jitter, UCIe, case management systems, DFT flows, AI-powered tools, Synthesis, Verilog RTL design

HDL - Verilog, Logic Design, Perl, shell scripting, System Verilog, Tcl, Synthesis, formal verification, low power design, Physical Design, EDA Tools, Timing Closure, digital ASICs, Genus Synthesis Solution

Developing Verification environments using System Verilog, Problem-solving and debugging, Verification and Design, UCIe domain, UVM methodology, Functional Verification