Transient Parasitic Management, Analog IC Design, GaN Device Physics, Layout Co-Extraction, Silicon-Device Co-Design, Calibre DRC, PEX, LVS, Mixed-signal IC Design, Spectre, Parasitics-aware Design, Bench Characterization and Debug, Double-pulse Testing, PEEC EM Extraction, Differential Probes, Cadence Virtuoso, Spectre21, High-speed High-voltage Gate Drivers, High-bandwidth Oscilloscopes

test validation , PLL Clock System Design, Layout Design, Low Current Mode, Transmitter Design, power management, Tape Out, Architecture Schematic Design, RF Transceiver Design, IF filter and VGA Design

Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout