Shell, Perl, Verilog, Python, Tcl, LINT, Makefiles, Cadence Xcelium, JasperGold Formal, Cadence VCS, QuestaSim, Uvm, systemverilog, Questa Formal, VHDL, Modelsim

Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis

Fpga, C, Soc Architecture, Verilog, Scripting Languages, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, ASIC design methodologies, low-power design techniques, emulation platforms, assertion-based formal verification

control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Python, FineSim, Synopsys VCS, Xcelium, Skill, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Timing Analysis, RTL Coding, Digital circuit design principles, Logic Synthesis, Simulation and verification methodologies, Debugging and troubleshooting complex digital systems, Power optimization techniques