reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso

Calibre, Mixed Signal Layout, Physical Verification, Analog Layout, DRC, Custom Layout, virtuoso, LVS, Chip Level Integration, CAD Tools, Layout Electrical Parameters

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

Vdc, custom analog layout design, EDA Tools, Antenna, ADC, Circuit Design, RV high voltage flows, noise fixes, LDO, layout validation, Charge pump, density, DRCs, scripting skills, Vlsi Design, Virtuoso XL