hardware bring up , Spi, Pcie, I2c, design tools including Cadence Concept, Ethernet high speed SERDES 25G interfaces, design validation, X86 architecture, SSD memory devices, MDIO, DDR5, Cadence Allegro

hardware bring up , Spi, Pcie, I2c, Ethernet high speed SERDES 25G interfaces, design validation, X86 architecture, Cadence Concept, SSD memory devices, MDIO, DDR5, Cadence Allegro

Functional Testing, Source code design, Certification according to RTCA DO-254, Qualification testing according to DO-160, Requirement generation, FPGA development life cycle, Test bench based verification, Board bring up testing, Schematic generation, Detailed design, Electronic product development, Schematic generation tools

hardware bring up , Spi, Pcie, I2c, design tools including Cadence Concept, Ethernet high speed SERDES 25G interfaces, design validation, X86 architecture, SSD memory devices, MDIO, DDR5, Cadence Allegro

boundary scan , Jtag, PLL testing, SSN, Uvm, systemverilog, Phy Loopback, DV, formal verification methods, compressed scan, agentic AI flows, Dft, memory BIST

I2c, Python, PCB back-end process, DFA, Logic Analyzers, LPDDR4 5, Buck and Boost PMIC, Oscilloscopes, PCIe interface Gen5 Gen6, LDO Load Switch devices, Dfm, SMBus, DC-DC converters, ONFI interface, Power Analyzers, I3C, NAND memories, PCIe analyzers