Python Scripting, Verilog, Gdb, SV-UVM, e-specman

C, Git, Shell, Perl, Python, Tcl, Xilinx FPGA, Siemens Veloce, Cadence Zebu, Palladium, Uvm, systemverilog, Vivado, SVA

Verilog, Sata, Python, Perl, Usb, Uvm, constrained random verification, functional coverage, PCI Express, systemverilog, VMM, DV methodologies

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

arm architecture , C, Firmware, Soc Architecture, Verilog, Embedded Software, Python, Perl, Assembly, CPU architecture, Emulation, systemverilog, AMBA protocols, Simulation

C, Debugging, Shell, Verilog, Tcl, System Verilog, Python, Perl, assertions, directed and constrained random methodologies, Uvm, Metric Driven Verification, formal verification methodologies