clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Perl, Debugging, Shell scripting, Python, Tcl, Uvm, Mixed-Signal Verification, systemverilog

Python, FineSim, Synopsys VCS, Xcelium, Skill, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Java, Rtos, C, Device Drivers, Memory Management, Yocto, Linux, Python, Virtualization Technologies, Automotive Grade Linux, ISO26262, Multiprocessor Architecture, ICE Debuggers, J-TAG

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL