Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

cache coherency , Verilog, Microarchitecture, Rtl Design, Digital Design, ip development

C, Pcie, Verilog, Sata, Matlab, System Verilog, Python, protocol analyzers, high-speed transceivers, HDL Simulation Tools, spectrum analyzers, FPGA tools, Axi, VHDL, Wishbone, Xilinx Vivado Design Suite, Avalon, high-speed oscilloscopes

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Uart, Spi, Can, Pcie, Verilog, I2c, Ddr3, Microchip Libero, MIL-STD-1553, Intel Quartus, SpaceFibre, systemverilog, Synopsys SpyGlass CDC, Xilinx Vivado, VHDL, SpaceWire, AXI4, Questa CDC

Rtl Design, high-speed interfaces, thermal monitoring integration, power management, clock-gating, systemverilog, embedded microcontroller integration, reset-domain architecture