Scripting Languages, Perl, Tcl, Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, SVRF rule decks, Calibre, Innovus, ICV, Design Rules, Mixed-signal SOC environments, Backend design methodologies, Tech LEF, Custom IC design flows, Layouts, ESD reliability analysis, PERC methodologies

Usb, Networking, Nvme, Storage, Graphics and Display, Python automation frameworks, Root Cause Analysis, Platform Validation, Post Silicon Validation, Platform Debug, System Debug, Platform security, RAS technologies, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions, DDR4 DDR5 Memory

Linux Os, Perl, Verilog, Python, Rtl Design, System Verilog based verification techniques, Specman e, SVTB, Simulation, Uvm, Emulation debug tools

Shell Scripts, Perl, Verilog, Ethernet, Python, Tcl, Design Verification, NIOS, logic simulations, ANLT, Rtl Design, VHDL, ASIC Design

power delivery , Ethernet, Raspberry Pi, Network Analyzers, x86 IPs, power management, Power Measurements, USB Type C, USB PD, Memory RAS, Memory DDR4 DDR5, LPDDR4 LPDDR5, Cores, Display interfaces, USB4.0 3.2 3.1, Post silicon validation

power delivery , Ethernet, Raspberry Pi, Network Analyzers, x86 IPs, power management, Power Measurements, USB Type C, USB PD, Memory RAS, Memory DDR4 DDR5, LPDDR4 LPDDR5, Cores, Display interfaces, USB4.0 3.2 3.1, Post silicon validation

Silicon Validation, Usb, Networking, Python automation frameworks, Post-silicon validation, DDR4 DDR5 Memory training and validation, Platform debug, Graphics and Display RAS technologies, Storage and NVMe, BIOS Firmware, Platform security, x86 platforms, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions