Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Perl, Ruby, System Verilog, make, Uvm, Asic verification, Rtl Design, formal verification, TestBench Development

UFS (Universal Flash Storage), C, C++, Makefile, Perl, Verilog, Ethernet, System Verilog, Verification tools such as VCS, System Verilog verification language, Uvm, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol

test environments , Test Cases, power-aware simulations, formal verification, DV testbenches, Design Verification, UVM methodology, power management features, coverage-driven verification, systemverilog