MATLAB, Shell, Logic Design, Octave, Verilog, Tcl, static timing analysis, Python, Debugging, Modelsim, Synthesis, place-and-route, Configuration Version control tools like SVN, XSIM, Zynq SoC, constraint management, Zynq UltraScale plus, Hardware Design, Xilinx tools for synthesis and implementation, RTL design in VHDL