Verilog, debug tools like Debussy GDB, bring-up lab debug, ASIC design flow, floor-planning, Timing Analysis, VCS or equivalent simulation tools, Eco, Rtl Design

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

C, Vcs, Verilog, Perl, formal verification, spyglass, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

Synthesis, micro-architecture specifications, Timing Closure, SoC integration, RTL code in Verilog, Verification, RTL logic design, timing optimization, assertions coverage analysis

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

Lsf, Unix, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, Python, GenAI, VLSI CAD, CI CD process, DesignSync, make, reinforcement learning, Design revision control, Dft, Design Verification, EDA Tools, Power-aware flows, Convolutional Networks, Graph Neural Networks