Shell, Perl, Debugging Tools, Python, verification methodologies, ASIC SOC verification, CPU GPU architecture or verification, Uvm, systemverilog

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

C, Jtag, Verilog, Scripting Languages, System Verilog, IEEE1500, HDLs, memory dump, advanced verification techniques, MBIST, scan dump, formal verification methodologies, CPU micro-architectures, Dft, CPU architectures, power management features

C, Fpga, Scripting, Verilog, coverage closure, Uvm, gate-level simulation, RTL testbench debugging, systemverilog, Emulation, subsystem integration, memory hierarchy, Arm CPU architecture, interrupts, coherency protocols, post-silicon validation

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Shell, Perl, Vcs, Python, Xcelium, Questa, CPU Processor verification, Uvm, systemverilog, SVA