Dsp, Gpu, C, Python, FP8, broadcast networks, PPA optimization, RTL SystemVerilog, output weight row-stationary, deep-learning operators, AI-accelerator micro-architecture, convolution, INT8, Rtl Design, mixed-precision, arithmetic FP32, matrix-multiply dataflows, sparsity acceleration techniques, compute datapath, BF16, AI compiler development, attention, high-throughput arithmetic datapaths, numerical formats, performance utilization models, GEMM, systolic spatial arrays