Job Title: FPGA Verification Engineer

Experience:5+ years

Job Location:Hyderabad, India

Job Summary:

We are looking for an experienced FPGA Verification Engineer with 5+ years of hands-on experience in FPGA verification, SystemVerilog, and UVM methodologies. The ideal candidate will be responsible for developing verification environments, executing verification plans, performing coverage analysis, and ensuring the quality of FPGA-based designs.

Key Responsibilities

Execute the complete FPGA verification flow from test planning to coverage closure.
Develop and maintain SystemVerilog/UVM-based testbenches.
Verify Ethernet protocols and other high-speed interfaces.
Perform functional and code coverage analysis to ensure design quality.
Debug simulation failures and work closely with design teams to resolve issues.
Develop automation scripts using TCL, Python, or Perl.
Analyze simulation results, waveforms, and verification metrics.
Collaborate with FPGA design, architecture, and validation teams throughout the development cycle.
Contribute to process improvements and verification automation initiatives.

Required Skills

5+ years of experience in FPGA Verification.
Strong knowledge of SystemVerilog and UVM.
Hands-on experience with Ethernet protocol verification and debugging.
Experience in code and functional coverage analysis.
Proficiency in TCL, Python, or Perl scripting.
Strong debugging and waveform analysis skills.
Experience with industry-standard simulation tools.
Good communication and problem-solving skills.

Preferred Skills

Exposure to AI-driven verification techniques and automation frameworks.
Experience with verification process optimization and tool automation.
Strong analytical and troubleshooting abilities.