Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, SDC knowledge, Fishtail, GCA, Synopsys Design Compiler, DMSA

synopsys primetime , Python, Tcl, PrimeTime-PX, PrimeTime-SI, POCV, crosstalk analysis, MCMM timing analysis, Cadence Tempus Timing Signoff Solution, AOCV

synopsys primetime , Routing, Perl, Python, Tcl, CTS, PTPX, Cadence Tempus, SDC, Synthesis, Eco, MMMC, Physical Design, STA Timing Closure, Digital Design

synopsys tools , .lib generation, python, perl, Tcl, STA tools, PD circuit simulation, ICC2

Static Timing Analysis, Design Compiler, primetime, Advanced technology nodes, Fusion Compiler, Synthesis flows, UPF, ECO flows, Scan and test-mode timing closure, Advanced constraint development, CPF, Low-power design, Clocking architectures, MMMC analysis

Embedded Software, C, Python, Soc Architecture, power characterization, hardware emulation

IC Compiler II, Yield Analysis, Timing Marginings, Monte Carlo simulations, PrimeTime SI PX, Design Compiler, Timing Closure, AOCV POCV SOCV analysis, IR drop analysis

design optimization, Logic Synthesis, Physical-aware RTL-to-gate synthesis, CDC-related timing issues, Timing Closure, PPA optimization, Post-route timing analysis, Formal equivalence checking, SDC constraints, ECO implementation, MMMC timing analysis