C, MATLAB, Perl, Python, RF ADE, systemverilog, Parasitic Extraction, Spectre, CMOS, SERDES, Cadence Virtuoso, Mixed-Signal Verification, Verilog-A

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

constraint random testing, coverage analysis, Uvm, scoreboards, checkers, formal verification, systemverilog, monitors

C Programming Language, Tcl Scripting, Embedded programming languages, Waveform viewers, Low level APIs on Microcontrollers, Simulators, Verification EDA Tools, Bare-metal programming

Python, Excel Vba, fatigue analysis, Ansys Workbench, Mathcad, Structural Analysis, Ansys Classic, Finite Element Analysis, Vibration Analysis, Classical Hand Calculations

python, Signal Processing, Reliability Testing, weibull analysis, risk identification, random failure principles, ALt, Electronics, Measurement, statistical reliability analysis, reliability engineering, Bayes theorem, Test-to-Failure, FIT rate estimation methodologies, FMEDA, halt, ?²-statistics, reliability prediction, reliability calculations, Sensors, accelerated stress testing, FTA, environmental validation, HAST

Tableau, Tcl, Powerbi, Ms Excel, Python, PERL, Ccsp, Sta, AOCV, EDA development, Layout Design, FinFET technologies, Standard Cell Circuit Design, RTL2GDS flow, NLDM, Circuit and MC simulations, LVF, characterization, PNR, Layout Dependent Effects, Skill, CCSN