Project Role : Design-For-Test (DFT) Engineer

Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills : Design for Testability (DFT)

Good to have skills : NA

Minimum 3 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary:

As a Design-For-Test Engineer, your day involves ensuring that integrated circuits are designed with features that facilitate thorough and efficient testing after manufacturing. You will focus on embedding testability elements within the design to identify potential defects early. Collaboration with various teams is essential to optimize the design for fault detection and isolation, thereby contributing to the production of high-quality silicon. Your role is pivotal in bridging design and testing processes to improve overall product reliability and performance.

Roles & Responsibilities:

Expected to perform independently and become an SME.
Required active participation/contribution in team discussions.
Contribute in providing solutions to work related problems.
Collaborate closely with cross-functional teams to ensure seamless integration of testability features.
Continuously analyze and improve test methodologies to enhance fault coverage and reduce test time.
Document design-for-test strategies and results to support knowledge sharing and process improvements.

Professional & Technical Skills:

Must To Have Skills: Proficiency in Design for Testability (DFT).
Strong understanding of scan chain insertion and optimization techniques.
Experience with Built-In Self-Test (BIST) implementation and boundary scan standards.
Ability to work with design and verification teams to enhance test coverage and fault isolation.
Familiarity with silicon debug and failure analysis processes.

Additional Information:

The candidate should have minimum 3 years of experience in Design for Testability (DFT).
This position is based at our BDC6F - SEZ office.
A 15 years full time education is required.